1. Field of the Invention
The present invention relates to a silicon carbide semiconductor substrate and a method of manufacturing the same.
2. Description of the Related Art
Since silicon carbide (SiC) has a larger band gap and a higher electric breakdown field than silicon (Si), it is expected to be applied to a semiconductor device (power device) for next generation power control. Even though it is known that silicon carbide has many crystal structures, 4H—SiC and 6H—SiC having a hexagonal crystal structure among these crystal structures are used to manufacture a practical power device.
Since there is a need to conduct a large current into a semiconductor device, many power devices have a structure where an electrode is installed on one surface and a rear surface of the device, respectively, to flow main current therebetween. Further, a need exists for a function to realize a state (turn-on state) where main current is conducted and a state (turn-off state) where main current is interrupted. In the turn-on state, it is important to reduce resistance (on-resistance), which is generated by conduction current, as much as possible such that a loss of the device can be reduced. Moreover, in the turn-off state, there is a need to maximally reduce leakage current with respect to a predetermined applied voltage.
In order for the power device to have the above-mentioned functions by using silicon carbide, the silicon carbide power device generally has a structure where an n-type silicon carbide single crystal wafer having a low resistance is used as a base substrate and a single crystal silicon carbide layer having a predetermined thickness and a donor concentration is formed on the base substrate by epitaxial growth. A basic structure of the semiconductor device including a p-n junction, etc., is made inside the silicon carbide epitaxial layer. The semiconductor device is optimally designed so that the epitaxial layer has high resistance, the donor concentration and thickness thereof satisfy a withstand voltage value, which is a specification of the device, and the on-resistance is small if possible. As such, the reason to use the epitaxial layer installed on the silicon carbide single crystal wafer in forming the device is that the required thickness of the high-resistance silicon carbide layer is a degree from several microns to several tens of microns, which is sufficiently thinner as compared to that of the high-resistance layer necessary for the device using silicon in the related art.
In developing the silicon carbide single crystal wafer, in order to make a diameter large and a length of a wafer ingot long, there is a need to make the surface thereof into a {0001} crystal plane. In the related art, when the silicon carbide single crystal layer is epitaxially grown on the {0001} crystal plane, there is a problem in that silicon carbide having a crystal type (polytype) different from the wafer is mixed. However, the problem is solved by making the surface of the epitaxially grown wafer into a surface inclined by several degrees from the {0001} crystal plane, making it possible to easily form the silicon carbide crystal layer having the same polytype as the wafer. The 4H—SiC wafer, which is being marketed currently, is a wafer whose {0001} crystal plane is inclined by 4° or 8°.
An attempt to improve the quality of the silicon carbide single crystal wafer while developing a technology of making the diameter thereof large has actively been progressed. However, linear single crystal structure defects called dislocations of 1000 to 10000 per square centimeter in the silicon carbide single crystal wafer still exist even in the present time. It has been known that the silicon carbide has three kinds of dislocations. These dislocations are threading screw dislocation and threading edge dislocation where a direction of a dislocation line is approximately perpendicular to the {0001} crystal plane and basal plane dislocation where a direction of a dislocation line is parallel with the {0001} crystal plane. Generally, the dislocations inside the crystal are specified by a Burgers vector and the direction of the dislocation line. The threading edge dislocation and the basal plane dislocation in the silicon carbide have the same Burgers vector, but they are distinguished by a difference in the direction of the dislocation line.
If one end of the dislocation line is exposed on the surface of the wafer, these dislocations in the silicon carbide single crystal wafer are inherited to the epitaxial growth layer when the silicon carbide single crystal layer is epitaxially grown on the wafer. When the wafer surface is parallel with the {0001} crystal plane, the basal plane dislocation is not inherited to the epitaxial growth layer without being exposed on the surface of the wafer. However, as described above, when the {0001} crystal plane inclines, a part of the basal plane dislocation on the plane is exposed on the surface of the wafer, such that it is propagated to the epitaxial growth layer. At this time, most of the propagated basal plane dislocations become the threading edge dislocation in the epitaxial growth layer by changing the direction of the dislocation line to a direction perpendicular to the {0001} crystal plane but about 10 to 20% of the basal plane dislocation exposed on the surface of the wafer is inherited into the epitaxial layer as the basal plane dislocation as it is, which is disclosed in pp 209 to 216, volume 260, Journal of Crystal Growth. On the other hand, the threading edge dislocation exposed on the surface of the wafer is propagated into the epitaxial layer as approximately 100% threading edge dislocation and the conversion from the threading edge dislocation into the basal plane dislocation is not almost generated, which is described in the same Journal of Crystal Growth.
Studies on any influence of the dislocations in the epitaxially grown silicon carbide on performance or reliability of the device have been actively progressed. Although the influence is not still completely understood, it is clear to be a cause that allows the basal plane dislocation in the epitaxial layer to increase on-resistance when a p-n junction diode is conducted for a long time, and to deteriorate reliability of a gate oxide film of a metal-oxide semiconductor field effect transistor (MOSFET). On the other hand, it is known that a part of the threading screw dislocation influences the device, but the details thereof are not clear. Further, the influence of the threading edge dislocation on the device has not been known until now. Therefore, it is preferable that the basal plane dislocation exists as small as possible or does not exist at all, if possible, in the epitaxial layer in which all structures of the device are made. For this reason, it is preferable to remarkably reduce the basal plane dislocation, if possible, in the silicon carbide single crystal wafer that is a substrate, but it is not yet an object to reduce dislocation density. Therefore, a technology to inherit the basal plane dislocation into the epitaxial layer itself while reducing a ratio thereof when the basal plane dislocation exposed on the surface the silicon carbide single crystal wafer is propagated to the epitaxial growth layer, that is, a technology to improve conversion efficiency from the basal plane dislocation into the threading edge dislocation when the basal plane dislocation of the wafer is propagated to the epitaxial growth layer has been considered as an important technology.